Modelling of Delay Lines on Pcbs
Designers of printed circuit boards often face the problem illustrated by the example in Figure 1.It is desired to transmit signals 1, 2 and 3 from one chip to the other with precisely the same transmission delay. However, with the routing pattern in Figure 1a, signal 3 has a longer path and will arrive later. The conventional solution, shown in Figure 1b, artificially extends the paths of signals 1 and 2 to match the lengths of all wires.
Traces such as those for signals 1 and 2 are called serpentine lines or meander lines. In the past, meander lines have been used with the assumption that the extra wire length is electrically identical to a straight section, and no parasitics were introduced. As trace dimensions become smaller and signal frequencies increase, that assumption may no longer be valid.
In this report, we present measurements of the time delay through, and characteristic impedance of meander lines as compared to an equivalent length of straight line.
It is seen that the delay through a meander line is shorter than the delay through an equivalent length of straight trace. This is because coupling between the segments of the meander lines shortens the electrical path.
The remainder of this report is organized as follows. Section 2 gives the physical background of transmission lines and meander lines, and defines terms used in the rest of the report. Section 3 discusses our measurement methods and reports experimental results. In Section 4, we discuss the results, and Section 5 gives a model for the observed effects. Finally, Section 6 gives conclusions.
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Electronics Engineering